It is known in the prior art that analog circuits can be adversely affected by layout characteristics in the nanometer technology. For example, some known proximity effects include well proximity, Shallow Trench Isolation (STI) stress, poly gate position effect, source/drain dimensional effect, channel length modulation, and narrow width effect. These impact of these proximity effects become greater as process technologies become smaller.
Various prior art solutions have been suggested to reduce these proximity effects in an analog circuit design. However, what is needed are analog circuit design techniques that take advantage of these proximity effects and use them to enhance the operation of analog circuit specifically for memory sensing circuitry. A split gate flash memory operation and various circuitry are described in U.S. Pat. No. 7,990,773, “Sub Volt Flash Memory System,” by Hieu Van Tran, et al, and U.S. Pat. No. 8,072,815, “Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and Systems,” by Hieu Van Tran, et al, which are incorporated herein by reference.